1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of thinning and/or separating semiconducting substrates having integrated circuit products formed thereon.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NFET and PFET transistors) represent one important type of circuit element that substantially determines performance of such integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NFET transistors and/or PFET transistors, are formed on a substrate including a crystalline semiconductor layer. In recent years, the device features of modern, ultrahigh density integrated circuits have been steadily decreasing in size in an effort to enhance the overall speed, performance and functionality of the circuit. As a result, the semiconductor industry has experienced tremendous growth due to the significant and ongoing improvements in integration density of a variety of electronic components, such as transistors, capacitors, diodes and the like. These improvements have primarily come about due to a persistent and successful effort to reduce the critical dimension—i.e., minimum feature size—of components, directly resulting in the ability of process designers to integrate more and more components into a given area of a semiconductor chip. As device features have been aggressively reduced, and more semiconductor components are being fit onto the surface of a single chip, the required number of electrical interconnects necessary for creating the “wiring” for the integrated circuit has dramatically increased. As a result, the overall circuit layout has become more complex and more densely-packed. Furthermore, even though improvements in photolithography processes have yielded significant increases in the integration densities of 2D circuit designs, simple reduction in feature size is rapidly approaching the limits of what can presently be achieved in only two dimensions.
As the number of electronic devices on a single chip rapidly increases, three-dimensional (3D) integrated circuit layouts, or stacked chip design, have been utilized for some semiconductor devices in an effort to overcome some of the feature size and density limitations associated with 2D layouts. Typically, in a 3D integrated circuit design, two or more semiconductor die are bonded together, and electrical connections are formed between each die. One method of facilitating the chip-to-chip electrical connections is by the use of so-called through-silicon vias, or TSV's. A TSV is a vertical electrical connection that passes completely through a silicon wafer or die, allowing for more simplified interconnection of vertically aligned electronic devices, thereby significantly reducing integrated circuit layout complexity as well as the overall dimensions of a multi-chip circuit. A typical TSV may have a diameter that falls within the range of 6-100 μm or smaller, and, as technology advances, there is constant pressure to make them even smaller. Similarly, there is a constant pressure to reduce the overall thickness of the wafers that are used in manufacturing semiconductor devices. In general, very little of the starting thickness of a semiconducting substrate is actually used in making semiconductor devices, i.e., the depth of the device regions in the substrate may be less than 10 μm. Thus, a large percentage of the starting thickness of the substrate is essentially not needed for the integrated circuit device to perform electrically. However, a certain amount of the thickness of the original wafer is maintained to ensure that the integrated circuit can mechanically withstand packaging operations and withstand the intended commercial environment for the integrated circuit product. In many applications, e.g., cell phones and other portable consumer electronic devices, it is desirable that the substrate in the integrated circuit product be made as thin as possible to reduce the physical size and weight of the final consumer product.
FIGS. 1A-1F depict one illustrative method of thinning an illustrative wafer 10 after a plurality of illustrative integrated circuit products 14 have been formed on the substrate 12. As shown in FIG. 1A, the substrate 12 has a front side 12F and a back side 12B. The integrated circuit products or die 14 are formed on the front side 12F of the substrate 12. Typically, the substrate 12 may have a starting thickness, as received from the wafer supplier, of about 775 μm. Ultimately, depending upon the particular application, prior to performing dicing operations to separate the plurality of die 14, the substrate 12 will be thinned to a final thickness that may fall within the range of about 20-200 μm. Typically, the die 14 are not formed on the very outer edge region 13 of the substrate 12, which may have a radial width of about 2 mm.
In this embodiment, as shown in FIG. 1B, the thinning process begins by using a dicing saw (not shown) and a schematically depicted dicing saw blade 16 to remove portions of the substrate 12 near the edge of the wafer 10. As depicted, the substrate 12 has curved outer edges 12C. In general, the spinning saw blade 16 is moved downward, as indicated by the arrow 16A, as the substrate 12 is rotated on a wafer stage (not shown). As shown in FIG. 1C, the process results in the formation of recesses 18 adjacent the edge of the substrate 12. The depth 18D and width 18W of the recesses 18 may vary depending upon the application and the final desired thickness of the substrate 12. Typically, the depth of the recesses 18 is slightly greater than the desired final thickness of the substrate 12. In one example, the depth 18D may fall within the range of about 100-400 μm and the width 18W may fall within the range of about 200-700 μm. In effect, the recesses 18 are formed to remove the curved outer edges 12C of the substrate 12 for a depth that is greater than the final desired thickness of the substrate 12.
Next, in this example, as shown in FIG. 1D, a layer of back grinding tape 20 is attached to the die 14 on the front side 12F of the wafer 10. Alternatively, a support wafer (not shown) could be attached to the front side 12F of the wafer 10 before grinding processes begin. Then, as shown in FIG. 1E, a schematically depicted grinding wheel 22 is used to grind the back side 12B of the substrate 12 to reduce the overall thickness of the substrate 12. FIG. 1F depicts the wafer 10 after the grinding process has been completed. At this point, the substrate 12 has a ground back surface 12BG and it has been thinned to a final desired thickness 12T. The final desired thickness 12T may range from about 20-100 μm depending upon the particular application, and further reductions in the final thickness 12T are anticipated for future generation devices. Next, as shown in FIG. 1G, the back grinding tape 20 has been removed and a layer of dicing tape 21 is attached to the ground back surface 12BG of the substrate 12. At the point of fabrication depicted in FIG. 1G, the dicing operations may be performed from the front side 12F of the substrate 12 to physically separate the illustrative die 14 formed on the substrate 12. Thereafter, the individual die are tested and packaged for commercial sale.
As wafers are thinned to final thicknesses of around 100 μm or less, there is an increased risk of chipping and cracking at the edge of the wafer. The edge trimming process described above in FIGS. 1B-1C is performed before the back-side grinding of the wafer in an effort to reduce the risk of generating cracks and chips at the edge of the wafer. However, the edge trimming process is generally a “dirty” process that creates many particles that may contaminate one or more of the die 14. Lastly, crystalline silicon wafers, the predominant form of semiconducting substrates used in manufacturing integrated circuit products, is typically a relatively brittle material wherein cracks or chips, once initiated, may, in some cases, propagate without an increase in the stress applied to the wafer.
The present disclosure is directed to various methods of thinning and/or separating semiconducting substrates having integrated circuit products formed thereon that may solve or reduce one or more of the problems identified above.